1. Technical Field of the Invention
The present invention relates to testing ferroelectric memory devices, and particularly to a test circuit and method for testing for effects of degradation of ferroelectric memory cells.
2. Description of the Related Art
Ferroelectricity is a phenomenon which can be observed in a relatively small class of dielectrics called ferroelectric materials. In a normal dielectric, upon the application of an electric field, positive and negative charges will be displaced from their original positionxe2x80x94a concept which is characterized by the dipole moment or polarization. This polarization or displacement will vanish, however, when the electric field returns back to zero. In a ferroelectric material, on the other hand, there is a spontaneous polarizationxe2x80x94a displacement which is inherent to the crystal structure of the material and does not disappear in the absence of the electric field. In addition, the direction of this polarization can be reversed or reoriented by applying an appropriate electric field.
These characteristics result in ferroelectric capacitors, formed from ferroelectric film or material disposed between parallel conduction plates, being capable of storing in a nonvolatile manner a first charge corresponding to a first polarization state in which the direction of polarization is in a first direction, and a second charge corresponding to a second polarization state in which the direction of polarization is in a second direction opposite the first direction. Ferroelectric capacitors are utilized in nonvolatile random access memory devices having a memory cell array architecture that is similar to the memory cell array architecture of dynamic random access memory (DRAM) devices.
In general terms, there are two types of ferroelectric memory cells. Referring to FIG. 1A, a one transistor, one capacitor (1T1C) memory cell utilizes a pass gate transistor T connected between a bit/column line BL and a first plate of ferroelectric capacitor C. A second plate of ferroelectric capacitor C is connected to a plate line P. The gate terminal of pass gate transistor T is connected to a word/row line W. A memory device utilizing a 1T1C memory cell uses a reference memory cell that is accessed at the same time the 1T1C memory cell is accessed so as to provide a charge differential appearing across a pair of bit lines coupled to the 1T1C cell and the reference cell. The use of 1T1C ferroelectric memory cells is known in the art.
Referring to FIG. 1B, a two transistor, two capacitor (2T2C) memory cell includes two ferroelectric capacitors C1 and C2. A first pass gate transistor T1 may be connected between a first plate of ferroelectric capacitor C1 and a first bit line BL of a bit line pair. A second pass gate transistor T2 may be connected between a first plate of ferroelectric capacitor C2 and a second bit line BLxe2x80x2 of the column line pair. A second plate of ferroelectric capacitors C1 and C2 may be connected to a plate line P. The gate terminal of pass gate transistors T1 and T2 may be connected to the word line W. Each capacitor C1 and C2 stores a charge representative of the polarization state thereof, the charge combining with the charge of the other capacitor to result in a charge differential appearing across bit lines BL and BLxe2x80x2 when the 2T2C memory cell is accessed. The polarity of the charge differential denotes the binary value stored by the 2T2C memory cell. The use of 2T2C ferroelectric memory cells is known in the art.
Referring now to FIG. 2, there is illustrated a timing diagram for the operation of a ferroelectric memory cell. As it should be understood that reading the value of a memory cell is destructive and the data value must be restored in the cell after the reading operation. When the plate is raised to a high logic value while the bit line is at a precharged low, the bit line gets charged by the switching charge of the cell while moving from a high logic value to a low logic value. The bit line charge differential may be used for the sensing operation as described herein above. The memory cell restoration takes place when the plate goes to a low logic value and the memory cell is driven to a high logic value and then finally back to its initial position when the bit line is driven to the low logic value.
A problem with ferroelectric memory devices is the existence of a phenomenon known as imprint. Imprint is a characteristic of ferroelectric films that refers to the tendency of a ferroelectric film/capacitor to prefer one polarization state over another polarization state. Imprint is known to occur when a ferroelectric capacitor is maintained in a single polarization state for a prolonged period of time. Imprint adversely effects the ability of a ferroelectric capacitor to switch between the polarization states. Consequently, the existence of imprint may directly impact the performance of a ferroelectric memory device.
The performance of ferroelectric memory cells has been seen to degrade over time due to a number of other phenomena as well. For instance, ferroelectric memory cells may be effected by fatigue, endurance, retaining data over time, etc. When holding data over a prolonged period of time, such as under accelerated conditions during burn-in, a ferroelectric memory cell maybe seen to degrade over the course of several hours or days. FIG. 3 shows how a ferroelectric memory cell may be degraded, with the polarization characteristic being shown for a normal ferroelectric memory cell in a continuous set of lines and the polarization characteristic being shown for a degraded ferroelectric memory cell in dashed lines. At some point, a memory cell exhibiting degraded performance may store a charge in its ferroelectric capacitor that cannot be accurately sensed by a sense amplifier, thereby rendering the memory cell incapable of storing data values.
It is inconvenient to accurately test the capability of a ferroelectric memory cell to hold a voltage level using conventional memory read operations, to determine whether a long term reliability risk exists with the memory cell. This is in part due to the fact a conventional memory read operation may only test whether or not the memory cell is operational and does not provide an indication of an extent or amount of degradation of the memory cell. Based upon the foregoing, there is a need to be able to more easily test the soundness of a ferroelectric memory to determine the reliability risk of the ferroelectric memory device.
Embodiments of the present invention are directed to a method and apparatus for testing the soundness of and determining the reliability risk in using a random access memory device, such as a ferroelectric random access memory device. The random access memory device includes an array of memory cells arranged in rows and columns associated with word lines and bit lines, respectively, sense amplifier circuitry selectively disabled during the testing of the random access memory device, address decode circuitry for selecting rows of memory cells within the array, and test circuitry for providing a current level corresponding to a voltage level appearing across the ferroelectric capacitor(s) of a memory cell connected to a selected bit line. Each bit line may be connected to and control the operating characteristics of a distinct transistor of the test circuitry, wherein each transistor is externally accessible when selected.
The testing of the random access memory device may be performed by connecting memory cells in an addressed row to the bit lines of the array. The sense amplifiers are disabled when the random access memory device is under test. The bit lines are sequentially selected and a current is provided to a test pad having a level that is proportional to the voltage of the selected bit line. Because the voltage of the selected bit line is proportional to the voltage across the capacitor(s) of the memory cell connected thereto, the current level provided to the test pad is indicative of the voltage maintained by the memory cell.
In determining the voltage level maintained by a selected memory cell, a mapping between the current level measured at the test pad and the voltage level of the selected bit line may be performed by a calibration circuit. The operating characteristics of the calibration circuit are substantially the same as the operating characteristics of the test circuitry. The mapping provides a relationship between a measured current and voltage applied to the calibration circuit which is substantially the same as the relationship between the current measured at the test pad and the voltage appearing at the selected bit line. The voltage at the bit line may be more accurately determined from the measured current at the test pad and the operating characteristics of the calibration circuit.